VLSI Design and Verification Trainer

About HCL GUVI

HCL GUVI (Grab Your Vernacular Imprint) is an HCL Group Company with over 3 million learners in 19 languages and partnerships with 1000+ hiring companies. Established in 2014 and acquired by the HCL Group in 2022, HCL GUVI aims to transcend language barriers in technology education by providing effective and high-quality learning and skilling programs. For more information, visit www.guvi.in.

Job Title: VLSI Design and Verification Trainer

Company: HCL GUVI

Location: Vietnam (Remote)

ASIC Design and Verification Mentor - Front END

Job Description: We are seeking a highly skilled and motivated ASIC Design and Verification Engineer to join our dynamic team. The successful candidate will be responsible for designing, implementing, and verifying complex ASIC designs for cutting-edge semiconductor products. This role requires expertise in digital design, verification methodologies, and proficiency in scripting and programming languages. Additionally, the candidate should possess strong problem-solving skills and the ability to work effectively in a collaborative environment.

Responsibilities:

• Architect and implement digital ASIC designs meeting performance, power, and area requirements.
• Develop and execute verification plans using industry-standard methodologies such as UVM (Universal Verification Methodology).
• Write and debug RTL (Register Transfer Level) code in Verilog/SystemVerilog.
• Create and maintain verification environments, including testbenches, models, and functional coverage.
• Collaborate with cross-functional teams including physical design, software, and validation to ensure successful tape-out.
• Analyze and debug simulation failures and work closely with design teams to resolve issues.
• Participate in design reviews, providing feedback and guidance to improve design quality and efficiency.
• Stay current with industry trends and advancements in ASIC design and verification methodologies.

Qualifications:

• Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Solid understanding of digital design fundamentals and ASIC design flow.
• Proficiency in Verilog/SystemVerilog and experience with ASIC design tools (Synopsys).
• Familiarity with verification methodologies such as UVM and scripting languages (e.g., Perl, Python).
• Experience with FPGA prototyping and emulation platforms is a plus.
• Strong analytical and problem-solving skills.
• Excellent communication and teamwork abilities.
• Ability to thrive in a fast-paced, dynamic environment.

Physical Design Mentor

Job Role: We are seeking an experienced Physical Design Mentor to provide guidance and mentorship to our team of physical design engineers. The ideal candidate will have extensive hands-on experience in all aspects of the physical design flow, including floorplanning, placement, routing, timing closure, and physical verification. This role requires strong leadership skills, excellent communication abilities, and a passion for developing talent within the organization.

Responsibilities:

• Mentor and coach junior physical design engineers, providing technical guidance and support throughout the design process.
• Review and provide feedback on floorplans, placement, and routing strategies to ensure optimal design quality and performance.
• Guide the team in achieving timing closure targets through effective timing analysis and optimization techniques.
• Collaborate with cross-functional teams including RTL design, verification, and backend implementation to address design challenges and meet project goals.
• Develop and maintain best practices, methodologies, and guidelines for physical design implementation.
• Stay current with industry trends and advancements in physical design methodologies and tools.
• Contribute to the continuous improvement of the physical design flow, identifying areas for optimization and efficiency gains.

Qualifications:

• Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Extensive experience in physical design implementation for complex ASIC designs.
• Proficiency in EDA tools such as Cadence Innovus, Synopsys ICC2, or similar tools.
• Strong understanding of deep sub-micron process technologies and associated physical design challenges.
• Excellent problem-solving skills and the ability to troubleshoot complex design issues.
• Effective communication and leadership abilities, with a track record of mentoring junior engineers.
• Proven ability to work collaboratively in a fast-paced, dynamic environment.

Location:

Vietnam

Skills: